Semiconductor component manufacturers are constantly striving to decrease the cost of manufacturing their products. One technique for reducing cost has been to shrink or reduce the lateral dimensions of the devices that make up the semiconductor components. In addition to shrinking the lateral dimensions, devices have been made even smaller by stacking metal interconnect layers that route signals to the various devices in the semiconductor component. The combination of shrinking and stacking has allowed manufacturers to increase the number of semiconductor components that can be manufactured from a single semiconductor wafer. These techniques have been especially beneficial for manufacturers of memory devices because these types of semiconductor components are formed as arrays that consume a large area of the semiconductor wafer. Shrinking the memory devices not only increases the number of memory components that can be manufactured from a single semiconductor wafer, but also decreases their access times.
In recent years memory device manufacturers have further increased the number of memory elements that can be made from a single semiconductor wafer by forming the memory elements above the semiconductor material containing the driver circuitry. For example, memory device manufacturers have used ferroelectric memory materials and polymeric memory materials disposed over a semiconductor material to form memory devices. Although these techniques have increased the number of memory elements that can be manufactured from a single semiconductor wafer, they have also increased the complexity and cost of manufacturing memory devices.
Accordingly, what is needed is a method for manufacturing the semiconductor memory device that is compatible with standard processing equipment and that is cost efficient.